Sr. Design Verification Engineer

Job Description

Job description

The candidate will have a key role in architecture and development of advanced verification environments for complex SoC components, while ensuring on time, one time best-in-class quality. The candidate will have a significant opportunity to interact with system design teams across geographies.

Job Requirements

·         An expert level with developing UVM-based SV test-benches.

·         Highly experienced with defining block, sub-system and SOC top level test plans

·         Analog mixed signal experience and analog modeling is a strong plus.

·         Relevant experience with one or more of PCIe, NVMe, NAND, DDR, and CPU sub-systems.

·         Work experience in I2C, USB 3.0, AXI, PCIe, SPI, Ethernet etc. desired

·         Deep understanding and knowledge of verification methodologies, flows and quality metrics.

·         Great debugging and problem-solving skills

·         Work closely with designers to resolve bugs

·         Team player with great interpersonal communication skills.

·         Having an entrepreneur's spirit for growing business an added plus

Job Qualifications

·         5-10+ years relevant experience in SoC verification.

·         1-2 years’ experience in leading a small team an added plus

·         Strong and relevant expertise with ASIC simulation tools and advanced verification methods.

·         Expert level in verification languages such as UVM and System Verilog.

·         Relevant experience with writing block-level and SoC test-plans

·         Scripting experience (Python/ Perl/ Tcl) a big plus